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| author | Anton Arapov <anton@redhat.com> | 2012-10-29 11:15:37 +0100 |
|---|---|---|
| committer | Anton Arapov <anton@redhat.com> | 2012-10-29 11:15:37 +0100 |
| commit | 7d558cd9c7b18e4b16953265aa0da45e63f3b968 (patch) | |
| tree | 7135d5a810768c9c619346282ee9cfdf1765e225 /arch/arm/boot/compressed/head.S | |
| parent | 985ef6b2108ed28ffd5f6630e1e0fce2e2a775f2 (diff) | |
| download | kernel-uprobes-7d558cd9c7b18e4b16953265aa0da45e63f3b968.tar.gz kernel-uprobes-7d558cd9c7b18e4b16953265aa0da45e63f3b968.tar.xz kernel-uprobes-7d558cd9c7b18e4b16953265aa0da45e63f3b968.zip | |
Signed-off-by: Anton Arapov <anton@redhat.com>
Diffstat (limited to 'arch/arm/boot/compressed/head.S')
| -rw-r--r-- | arch/arm/boot/compressed/head.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index b8c64b80baf..bc67cbff394 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -653,16 +653,21 @@ __armv7_mmu_cache_on: mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs #endif mrc p15, 0, r0, c1, c0, 0 @ read control reg + bic r0, r0, #1 << 28 @ clear SCTLR.TRE orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement orr r0, r0, #0x003c @ write buffer #ifdef CONFIG_MMU #ifdef CONFIG_CPU_ENDIAN_BE8 orr r0, r0, #1 << 25 @ big-endian page tables #endif + mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg orrne r0, r0, #1 @ MMU enabled movne r1, #0xfffffffd @ domain 0 = client + bic r6, r6, #1 << 31 @ 32-bit translation system + bic r6, r6, #3 << 0 @ use only ttbr0 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer mcrne p15, 0, r1, c3, c0, 0 @ load domain access control + mcrne p15, 0, r6, c2, c0, 2 @ load ttb control #endif mcr p15, 0, r0, c7, c5, 4 @ ISB mcr p15, 0, r0, c1, c0, 0 @ load control register |