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| author | Anton Arapov <anton@redhat.com> | 2012-10-29 11:15:37 +0100 |
|---|---|---|
| committer | Anton Arapov <anton@redhat.com> | 2012-10-29 11:15:37 +0100 |
| commit | 7d558cd9c7b18e4b16953265aa0da45e63f3b968 (patch) | |
| tree | 7135d5a810768c9c619346282ee9cfdf1765e225 /Documentation/devicetree/bindings/arm/calxeda | |
| parent | 985ef6b2108ed28ffd5f6630e1e0fce2e2a775f2 (diff) | |
| download | kernel-uprobes-7d558cd9c7b18e4b16953265aa0da45e63f3b968.tar.gz kernel-uprobes-7d558cd9c7b18e4b16953265aa0da45e63f3b968.tar.xz kernel-uprobes-7d558cd9c7b18e4b16953265aa0da45e63f3b968.zip | |
Signed-off-by: Anton Arapov <anton@redhat.com>
Diffstat (limited to 'Documentation/devicetree/bindings/arm/calxeda')
3 files changed, 46 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/calxeda/combophy.txt b/Documentation/devicetree/bindings/arm/calxeda/combophy.txt new file mode 100644 index 00000000000..6622bdb2e8b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/calxeda/combophy.txt @@ -0,0 +1,17 @@ +Calxeda Highbank Combination Phys for SATA + +Properties: +- compatible : Should be "calxeda,hb-combophy" +- #phy-cells: Should be 1. +- reg : Address and size for Combination Phy registers. +- phydev: device ID for programming the combophy. + +Example: + + combophy5: combo-phy@fff5d000 { + compatible = "calxeda,hb-combophy"; + #phy-cells = <1>; + reg = <0xfff5d000 0x1000>; + phydev = <31>; + }; + diff --git a/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt new file mode 100644 index 00000000000..94e642a33db --- /dev/null +++ b/Documentation/devicetree/bindings/arm/calxeda/l2ecc.txt @@ -0,0 +1,15 @@ +Calxeda Highbank L2 cache ECC + +Properties: +- compatible : Should be "calxeda,hb-sregs-l2-ecc" +- reg : Address and size for ECC error interrupt clear registers. +- interrupts : Should be single bit error interrupt, then double bit error + interrupt. + +Example: + + sregs@fff3c200 { + compatible = "calxeda,hb-sregs-l2-ecc"; + reg = <0xfff3c200 0x100>; + interrupts = <0 71 4 0 72 4>; + }; diff --git a/Documentation/devicetree/bindings/arm/calxeda/mem-ctrlr.txt b/Documentation/devicetree/bindings/arm/calxeda/mem-ctrlr.txt new file mode 100644 index 00000000000..f770ac0893d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/calxeda/mem-ctrlr.txt @@ -0,0 +1,14 @@ +Calxeda DDR memory controller + +Properties: +- compatible : Should be "calxeda,hb-ddr-ctrl" +- reg : Address and size for DDR controller registers. +- interrupts : Interrupt for DDR controller. + +Example: + + memory-controller@fff00000 { + compatible = "calxeda,hb-ddr-ctrl"; + reg = <0xfff00000 0x1000>; + interrupts = <0 91 4>; + }; |