From a47abd7bf4b87e4bd5cbdaf88bbece6810d8c837 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Sat, 1 May 2021 17:05:26 +0200 Subject: Revert "fdt: translate address if #size-cells = <0>" This reverts commit d64b9cdcd475eb7f07b49741ded87e24dae4a5fc. As pointed by [1] and [2], the reverted patch made every DT 'reg' property translatable. What the patch was trying to fix was fixed in a different way from previously submitted patches which instead of correcting the generic address translation function fixed the issue with appropriate platform code. [1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/ [2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/ Signed-off-by: Dario Binacchi Reviewed-by: Bin Meng --- include/asm-generic/global_data.h | 24 ------------------------ 1 file changed, 24 deletions(-) (limited to 'include') diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index e1a5f4b1d1..47921d27b1 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -183,12 +183,6 @@ struct global_data { struct global_data *new_gd; #ifdef CONFIG_DM - /** - * @dm_flags: additional flags for Driver Model - * - * See &enum gd_dm_flags - */ - unsigned long dm_flags; /** * @dm_root: root instance for Driver Model */ @@ -519,12 +513,6 @@ struct global_data { #define gd_acpi_ctx() NULL #endif -#if CONFIG_IS_ENABLED(DM) -#define gd_size_cells_0() (gd->dm_flags & GD_DM_FLG_SIZE_CELLS_0) -#else -#define gd_size_cells_0() (0) -#endif - /** * enum gd_flags - global data flags * @@ -609,18 +597,6 @@ enum gd_flags { GD_FLG_SMP_READY = 0x40000, }; -/** - * enum gd_dm_flags - global data flags for Driver Model - * - * See field dm_flags of &struct global_data. - */ -enum gd_dm_flags { - /** - * @GD_DM_FLG_SIZE_CELLS_0: Enable #size-cells=<0> translation - */ - GD_DM_FLG_SIZE_CELLS_0 = 0x00001, -}; - #endif /* __ASSEMBLY__ */ #endif /* __ASM_GENERIC_GBL_DATA_H */ -- cgit From 33b7258947f4a15a048f7c31c3f5d72221152ba2 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Fri, 23 Apr 2021 11:27:42 -0500 Subject: board: ti: am64x: Add board support for am64x evm Add board specific initialization for am64x based boards. Signed-off-by: Dave Gerlach --- include/configs/am64x_evm.h | 105 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 include/configs/am64x_evm.h (limited to 'include') diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h new file mode 100644 index 0000000000..99c779b584 --- /dev/null +++ b/include/configs/am64x_evm.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for K3 AM642 SoC family + * + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Keerthy + */ + +#ifndef __CONFIG_AM642_EVM_H +#define __CONFIG_AM642_EVM_H + +#include +#include +#include + +/* DDR Configuration */ +#define CONFIG_SYS_SDRAM_BASE1 0x880000000 + +#ifdef CONFIG_SYS_K3_SPL_ATF +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" +#endif + +#ifndef CONFIG_CPU_V7R +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ + CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE - 4) +/* + * Maximum size in memory allocated to the SPL BSS. Keep it as tight as + * possible (to allow the build to go through), as this directly affects + * our memory footprint. The less we use for BSS the more we have available + * for everything else. + */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x5000 +/* + * Link BSS to be within SPL in a dedicated region located near the top of + * the MCU SRAM, this way making it available also before relocation. Note + * that we are not using the actual top of the MCU SRAM as there is a memory + * location filled in by the boot ROM that we want to read out without any + * interference from the C context. + */ +#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\ + CONFIG_SPL_BSS_MAX_SIZE) +/* Configure R5 SPL post-relocation malloc pool in DDR */ +#define CONFIG_SYS_SPL_MALLOC_START 0x84000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M + +#define PARTS_DEFAULT \ + /* Linux partitions */ \ + "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" + +/* U-Boot general configuration */ +#define EXTRA_ENV_AM642_BOARD_SETTINGS \ + "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "findfdt=" \ + "setenv name_fdt ${default_device_tree};" \ + "setenv fdtfile ${name_fdt}\0" \ + "name_kern=Image\0" \ + "console=ttyS2,115200n8\0" \ + "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 " \ + "${mtdparts}\0" \ + "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0" + +/* U-Boot MMC-specific configuration */ +#define EXTRA_ENV_AM642_BOARD_SETTINGS_MMC \ + "boot=mmc\0" \ + "mmcdev=1\0" \ + "bootpart=1:2\0" \ + "bootdir=/boot\0" \ + "rd_spec=-\0" \ + "init_mmc=run args_all args_mmc\0" \ + "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \ + "get_overlay_mmc=" \ + "fdt address ${fdtaddr};" \ + "fdt resize 0x100000;" \ + "for overlay in $name_overlays;" \ + "do;" \ + "load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && " \ + "fdt apply ${dtboaddr};" \ + "done;\0" \ + "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \ + "${bootdir}/${name_kern}\0" \ + "get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \ + "${bootdir}/${name_fit}\0" \ + "partitions=" PARTS_DEFAULT + +/* Incorporate settings into the U-Boot environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ + EXTRA_ENV_AM642_BOARD_SETTINGS \ + EXTRA_ENV_AM642_BOARD_SETTINGS_MMC + +/* Now for the remaining common defines */ +#include + +/* MMC ENV related defines */ +#ifdef CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 1 +#endif + +#endif /* __CONFIG_AM642_EVM_H */ -- cgit From dd41886498f35e2f0d2e6e30e9b021e832beb4d2 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Fri, 23 Apr 2021 11:27:43 -0500 Subject: dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM64 Add pinctrl macros for AM64 SoC. These macro definitions are similar to that of previous platforms, but adding new definitions to avoid any naming confusions in the soc dts files. Signed-off-by: Dave Gerlach --- include/dt-bindings/pinctrl/k3.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h index ce0cd38f56..e6cb1d0540 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -2,7 +2,7 @@ /* * This header provides constants for TI K3-AM65 pinctrl bindings. * - * Copyright (C) 2018 Texas Instruments + * Copyright (C) 2018-2021 Texas Instruments */ #ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM65_H #define _DT_BINDINGS_PINCTRL_TI_K3_AM65_H @@ -38,4 +38,7 @@ #define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #endif -- cgit From aad1614468e900771051701f46b0f93656dda698 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 6 May 2021 16:44:53 +0530 Subject: include: configs: am64x: Avoid overlap of BSS and stack area Avoid R5 SPL stack writing into ROM index table. Re-use the same space for storing EEPROM data. Signed-off-by: Lokesh Vutla --- include/configs/am64x_evm.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 99c779b584..5d756b409d 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -25,8 +25,10 @@ #endif #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE +#if defined(CONFIG_TARGET_AM642_A53_EVM) #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE - 4) +#else /* * Maximum size in memory allocated to the SPL BSS. Keep it as tight as * possible (to allow the build to go through), as this directly affects @@ -43,9 +45,12 @@ */ #define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\ CONFIG_SPL_BSS_MAX_SIZE) +/* Set the stack right below the SPL BSS section */ +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR /* Configure R5 SPL post-relocation malloc pool in DDR */ #define CONFIG_SYS_SPL_MALLOC_START 0x84000000 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M +#endif #define PARTS_DEFAULT \ /* Linux partitions */ \ -- cgit From 212cba02b7db8635ae45c97e99dcb8020bfebc9b Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 6 May 2021 16:44:54 +0530 Subject: include: configs: am64x_evm: Optimize size of SPL BSS Current BSS allocation of SPL is as below: size spl/u-boot-spl text data bss dec hex filename 144572 5484 1752 151808 25100 spl/u-boot-spl But 20KB is allocated currently for BSS. Reduce it to 4KB and save some space for stack. Signed-off-by: Lokesh Vutla --- include/configs/am64x_evm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 5d756b409d..6fe5c19f12 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -35,7 +35,7 @@ * our memory footprint. The less we use for BSS the more we have available * for everything else. */ -#define CONFIG_SPL_BSS_MAX_SIZE 0x5000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* * Link BSS to be within SPL in a dedicated region located near the top of * the MCU SRAM, this way making it available also before relocation. Note -- cgit From 5af71f265854e7280c07cd4df26250ef54b7dcb2 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 6 May 2021 16:44:55 +0530 Subject: include: configs: Update env for selecting right dtb Now that single defconfig can be used for booting AM64 EVM and SK, default device tree will not work for selecting dtb for kernel. Update the env to select right dtb based on eeprom. Signed-off-by: Lokesh Vutla --- include/configs/am64x_evm.h | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 6fe5c19f12..7c30e50c5f 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -58,10 +58,13 @@ /* U-Boot general configuration */ #define EXTRA_ENV_AM642_BOARD_SETTINGS \ - "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "findfdt=" \ - "setenv name_fdt ${default_device_tree};" \ - "setenv fdtfile ${name_fdt}\0" \ + "if test $board_name = am64x_gpevm; then " \ + "setenv fdtfile k3-am642-evm.dtb; fi; " \ + "if test $board_name = am64x_skevm; then " \ + "setenv fdtfile k3-am642-sk.dtb; fi;" \ + "if test $fdtfile = undefined; then " \ + "echo WARNING: Could not determine device tree to use; fi; \0" \ "name_kern=Image\0" \ "console=ttyS2,115200n8\0" \ "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 " \ @@ -76,7 +79,7 @@ "bootdir=/boot\0" \ "rd_spec=-\0" \ "init_mmc=run args_all args_mmc\0" \ - "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \ + "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ "get_overlay_mmc=" \ "fdt address ${fdtaddr};" \ "fdt resize 0x100000;" \ -- cgit From 91f1e792fe085cd14919803b55983b8c760effb0 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Mon, 10 May 2021 20:06:02 +0530 Subject: firmware: ti_sci: Update ti_sci_cmd_rm_udmap_tx_ch_cfg() API to the latest Update struct ti_sci_msg_rm_udmap_tx_ch_cfg_req to latest ABI to support AM64x BCDMA Block copy channels. Signed-off-by: Vignesh Raghavendra --- include/linux/soc/ti/ti_sci_protocol.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include') diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h index eb916ba101..794737923c 100644 --- a/include/linux/soc/ti/ti_sci_protocol.h +++ b/include/linux/soc/ti/ti_sci_protocol.h @@ -379,6 +379,13 @@ struct ti_sci_rm_psil_ops { #define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0 #define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2 +#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES 1 +#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES 2 +#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES 3 + +#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_TCHAN 0 +#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN 1 + /* UDMAP TX/RX channel valid_params common declarations */ #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0) #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1) @@ -389,6 +396,7 @@ struct ti_sci_rm_psil_ops { #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6) #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7) #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID BIT(14) /** * Configures a Navigator Subsystem UDMAP transmit channel @@ -403,6 +411,8 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg { #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11) #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12) #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID BIT(15) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID BIT(16) u16 nav_id; u16 index; u8 tx_pause_on_err; @@ -419,6 +429,9 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg { u8 tx_orderid; u16 fdepth; u8 tx_sched_priority; + u8 tx_burst_size; + u8 tx_tdtype; + u8 extended_ch_type; }; /** @@ -448,6 +461,7 @@ struct ti_sci_msg_rm_udmap_rx_ch_cfg { u8 rx_chan_type; u8 rx_ignore_short; u8 rx_ignore_long; + u8 rx_burst_size; }; /** -- cgit From c409b4932dba6403a706f9453d627abfb5d93e20 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Mon, 10 May 2021 20:06:03 +0530 Subject: soc: ti: k3-navss-ringacc: Add AM64 ringacc support AM64 dual mode rings are modeled as pair of Rings objects which has common configuration and memory buffer, but separate real-time control register sets for each direction mem2dev (forward) and dev2mem (reverse). AM64 rings must be requested only using k3_ringacc_request_rings_pair(), and forward ring must always be initialized/configured. After this any other Ringacc APIs can be used without any callers changes. Signed-off-by: Vignesh Raghavendra --- include/linux/soc/ti/k3-navss-ringacc.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'include') diff --git a/include/linux/soc/ti/k3-navss-ringacc.h b/include/linux/soc/ti/k3-navss-ringacc.h index 9176277ff0..1e9b7d9125 100644 --- a/include/linux/soc/ti/k3-navss-ringacc.h +++ b/include/linux/soc/ti/k3-navss-ringacc.h @@ -238,4 +238,19 @@ int k3_nav_ringacc_ring_push_head(struct k3_nav_ring *ring, void *elem); */ int k3_nav_ringacc_ring_pop_tail(struct k3_nav_ring *ring, void *elem); +/* DMA ring support */ +struct ti_sci_handle; + +/** + * struct struct k3_ringacc_init_data - Initialization data for DMA rings + */ +struct k3_ringacc_init_data { + const struct ti_sci_handle *tisci; + u32 tisci_dev_id; + u32 num_rings; +}; + +struct k3_nav_ringacc *k3_ringacc_dmarings_init(struct udevice *dev, + struct k3_ringacc_init_data *data); + #endif /* __SOC_TI_K3_NAVSS_RINGACC_API_H_ */ -- cgit From f1e97c705803ab07141640238a9c3036daf03011 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Mon, 10 May 2021 20:06:04 +0530 Subject: soc: ti: k3-navss-ringacc: Remove unused ring modes With AM64x supporting only K3_NAV_RINGACC_RING_MODE_RING or the exposed ring mode, all other K3 SoCs have also been moved to this common baseline. Therefore drop other modes such as K3_NAV_RINGACC_RING_MODE_MESSAGE (and proxy) to save on SPL footprint. There is a saving of ~800 bytes with this change for am65x_evm_r5_defconfig. Signed-off-by: Vignesh Raghavendra Reviewed-by: Grygorii Strashko --- include/linux/soc/ti/k3-navss-ringacc.h | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'include') diff --git a/include/linux/soc/ti/k3-navss-ringacc.h b/include/linux/soc/ti/k3-navss-ringacc.h index 1e9b7d9125..0ad8f203da 100644 --- a/include/linux/soc/ti/k3-navss-ringacc.h +++ b/include/linux/soc/ti/k3-navss-ringacc.h @@ -83,22 +83,17 @@ struct k3_nav_ring_cfg { }; #define K3_NAV_RINGACC_RING_ID_ANY (-1) -#define K3_NAV_RINGACC_RING_USE_PROXY BIT(1) /** * k3_nav_ringacc_request_ring - request ring from ringacc * @ringacc: pointer on ringacc * @id: ring id or K3_NAV_RINGACC_RING_ID_ANY for any general purpose ring - * @flags: - * @K3_NAV_RINGACC_RING_USE_PROXY: if set - proxy will be allocated and - * used to access ring memory. Sopported only for rings in - * Message/Credentials/Queue mode. * * Returns pointer on the Ring - struct k3_nav_ring * or NULL in case of failure. */ struct k3_nav_ring *k3_nav_ringacc_request_ring(struct k3_nav_ringacc *ringacc, - int id, u32 flags); + int id); int k3_nav_ringacc_request_rings_pair(struct k3_nav_ringacc *ringacc, int fwd_id, int compl_id, -- cgit